Conventional multi-die semiconductor packages are organized internally about Cartesian coordinates. One consequence of the Cartesian organization is that some traces on the substrate follow long and complex routes. With the Cartesian approach, the routing becomes unnecessarily long due to large distances between pads on different dies that are not on edges facing each other. The non-facing pad situation complicates and lengthens routes and causes increased signal propagation delays.
A large number of long traces on the substrate commonly reduces available space for routing. The reduced available space potentially causes difficulty in substrate designs where a number of traces are required, such as feature-rich devices. In some cases, a larger package size is required to accommodate the inefficient routing, thus increasing signal delays. As more and more multi-chip products are being made and the dies involved become more complicated and require large amounts of inter-connections, a reliable, automated, efficient way of determining optimal die orientation is important to ensure that the package substrate design is optimal and without unnecessary iterations.